Digital Logic - Autumn 2019
Course Information:
Outline
Course Syllabus
School of Engineering Homework Standards
D2L
Lecture:
Homework:
- #1 (Number Systems, Due Wed, 9/25)
- #2 (Chapter 2 - Part I, Due Mon, 9/30)
- #3 (Chapter 2 - Part II, Due Wed, 10/2)
- #4 (Chapter 4 - Part I, Due Mon, 10/7)
- #5 (Chapter 4 - Part II, Due Wed, 10/9)
- #6 (Logic Board Construction and Debugging, Due Fri, 10/18)
- #7 (Multiplexer Circuits, Due Fri, 10/18)
- #8 (Decoder Circuits, Due Wed, 10/23)
- #9 (Chapter 7 - Latch Design, Due Fri, 11/1)
- #10 (Chapter 7 - Latch Construction, Due Mon, 11/4)
- #11 (State Machine Design - Part I, Due Wed, 11/6)
- #12 (State Machine Design - Part II, Due Fri, 11/8)
- #13 (State Machine Design - Part III, Due Mon, 11/11)
- #14 (State Machine Design - Alternative Architectures, Due Fri, 11/15)
- #15 (Counter Circuits, Due Mon, 11/18)
Datasheets:
Tests:
Project:
Simulators:
Logic Board: